Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis
نویسندگان
چکیده
منابع مشابه
Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical-Thermal-Mechanical Coupling
A robust physical design of 3D-IC requires investigation on through-silicon-via (TSV). The large temperature and stress gradients can severely affect TSV delay with large variation. The traditional physical model treats TSV as resistor with linear electrical-thermal dependence, which ignores the fundamental device physics. In this paper, a physics-based electrical-thermal-mechanical delay model...
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ژورنال
عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
سال: 2015
ISSN: 1063-8210,1557-9999
DOI: 10.1109/tvlsi.2014.2354347